1. Field of the Invention
The present invention generally relates to contact structure for interconnection in semiconductor devices and manufacturing methods thereof. More particularly, the present invention relates to improvements in a contact structure for interconnection in semiconductor integrated circuit devices which provides through a contact hole electrical contact between an interconnection layer and a conductive region formed in a semiconductor substrate, and in a manufacturing method thereof.
2. Description of the Background Art
FIGS. 9A to 9F are fragmentary sectional views showing in particular a method of forming a contact structure for interconnection in a conventional manufacturing method of semiconductor devices, along its process flow. FIG. 10A is a plan view corresponding to FIG. 9B, which shows a sectional view along IX--IX in FIG. 10A. FIG. 10B is a plan view corresponding to FIG. 9E which shows a sectional view along IX--IX in FIG. 10B. Referring to these diagrams, a conventional method of forming a contact structure for interconnection in semiconductor devices will be described. Now, a dynamic random access memory (DRAM) having a planar capacitor structure will be taken as an example of semiconductor devices in describing a method of forming a contact structure for interconnection therein.
First, referring to FIG. 9A, a p-type impurity-diffused region 15 for preventing inversion and a thick isolating oxide film 14 are formed by thermally oxidizing a p-type silicon substrate 1 which has had p-type impurity ions selectively implanted therein. N-type impurity ions are then implanted by ion implantation method or the like, and a heat treatment is applied to form an n-type impurity-diffused region 16. Thereafter, a thin capacitor gate insulating film 17 is formed by thermal oxidation or chemical vapor deposition (CVD) method. Over this capacitor gate insulating film 17, a polycrystalline silicon layer containing impurities of a predetermined conductivity-type is deposited by CVD method or the like, and selectively removed by photolithography to form a cell plate 18. Thus, a capacitor comprised of n-type impurity-diffused region 16 and cell plate 18 is formed.
A gate oxide film 12 is formed on p-type silicon substrate 1 by thermal oxidation or the like. A polycrystalline silicon monolayer film or a two-layer film of polycrystalline silicon and metal silicide having a high melting point is deposited on gate oxide film 12 by CVD method or the like. Thereafter, those films are selectively removed by photolithography or the like, leaving gate electrodes 11 formed apart from each other. Phosphorus ions, n-type impurities are implanted into silicon substrate 1 by ion implantation method or the like, using gate electrodes 11 and cell plates 18 as mask. Thereafter, n-type impurity-diffused regions 13 are formed as source/drain regions of MOS transistors by application of a thermal treatment. At this time, one of paired n-type impurity-diffused regions 13 is formed to be connected to n-type impurity-diffused region 16 constituting a capacitor.
Subsequently, referring to FIG. 9B, an insulating oxide film 2 is deposited over the entire surface of the substrate by low pressure CVD or the like, and then selectively removed by photolithography, forming a contact hole 3. This contact hole 3 is formed by selectively etching away insulating oxide film 2 with selective etching technique including isotropic wet etching and anisotropic reactive ion etching (RIE), using a predetermined resist pattern formed thereon as mask. FIG. 10A is a plan view showing arrangement of thus formed contact holes 3.
As shown in FIG. 9C, undoped polycrystalline silicon film 9 is deposited by low pressure CVD method to have a thickness of 1000 to 1500 .ANG. on exposed surfaces of impurity-diffused regions 13, or drain/source regions, and over insulating oxide film 2.
As shown in FIG. 9D, in order to reduce resistance of this undoped polycrystalline silicon film 9, phosphorous of n-type impurity is thermally diffused into the surface of undoped polycrystalline silicon film 9 in the direction indicated by arrow 7. At this time, the thermal diffusion is carried out at a temperature of 900.degree. C. such that polycrystalline silicon film 91 has an impurity concentration of about 10.sup.22 /cm.sup.3. At the same time, an impurity-diffused region 10 is formed also in silicon substrate 1 through polycrystalline silicon film 91 to get contact with an impurity diffused region 13. In this manner, electrical contact is made between polycrystalline silicon film 91 which contains impurities and serves as an interconnection layer and the impurity-diffused region 13, or source/drain region, through impurity-diffused region 10.
Meanwhile, in the step shown in FIG. 9C, a doped polycrystalline silicon film may be formed. In this case, the thermal diffusion for the polycrystalline silicon film containing n-type impurities as shown in FIG. 9D is not carried out. The impurities with which the polycrystalline silicon film is doped are thermally diffused in a heat treatment applied in a later step so that impurity-diffused region 10 for taking contact with an impurity-diffused region 13 is formed.
Referring to FIG. 9E, a metal silicide film 92 having a high melting point is formed on polycrystalline silicon film 91. In this manner, a bit line constituted of polycrystalline silicon film 91 and metal silicide film 92 of a high melting point is connected to the other impurity-diffused region 13. Thereafter, a thick interlayer insulating film 20 is formed. A plan view showing arrangement of bit lines is given by FIG. 10B.
Referring to FIG. 9F, an aluminum layer is deposited over interlayer insulating film 20 by sputtering. Thereafter, the aluminum layer is patterned by photolithography such that an aluminum interconnection layer 50 is formed to serve as auxiliary word lines which extend in the direction parallel to gate electrodes 11 serving as word lines.
In the conventional contact structure for interconnection, however, the thermal diffusion of impurities from the polycrystalline silicon film entails undesirably extensive diffusion into the silicon substrate, especially in a lateral direction. In FIG. 9F, for example, when the thermal diffusion of impurities is carried out under such conditions as described above, impurity-diffused region 10 for contact acquires a dimension with l1 of about 0.2 .mu.m and d of about 0.5 .mu.m. Thus, the lateral length of impurity-diffused region 10 may possibly exceed the diameter of a contact hole. This has emerged as a significant problem for the increasingly miniaturized semiconductor devices of recent years. That is, in FIG. 9F, as the semiconductor device is miniaturized, the distance between gate electrodes 11 is diminished so that the distance ;2 between a sidewall surface of insulating oxide film 2 which defines dimension of the contact hole and a sidewall surface of a gate electrode 11 is reduced to about 0.5 .mu.m. Accordingly, the lateral extension l1 of impurity-diffused region 10 for contact may adversely affect an impurity-diffused region 13 serving as a source/drain region of an MOS transistor. As a result, it becomes difficult to secure a marginal region which is necessary to maintain specific characteristics of the MOS transistor.
The above-mentioned problem concerning the difficulty of securing a marginal region is understandable especially in the case that errors have occured in the patterning for forming contact holes. FIG. 11 shows a sectional view of a contact structure for interconnection where no error has occurred in the patterning for forming contact holes, and a diagram showing distribution of impurity concentrations corresponding to the sectional view. FIG. 12 shows a sectional view of a contact structure for interconnection where errors have occurred in the patterning for forming contact holes, and a diagram showing distribution of impurity concentrations corresponding the sectional view. Referring to those diagrams, problems that arise when errors have occurred in the patterning will be described below.
As shown in FIG. 11, gate electrode 111 is formed on p-type silicon substrate 1 with gate oxide film 112 interposed therebetween. On a sidewall of gate electrode 111, there is formed sidewall insulating film 210 Impurity-diffused region 213 having a low concentration of no more than 10.sup.19 /cm is formed in silicon substrate 1 beneath sidewall insulating film 210. Another impurity-diffused region 113 having a high concentration of about 10.sup.20 /cm is formed to be connected to impurity-diffused region 213 of a low concentration. Such a structure of impurity-diffused regions is called LDD (Lightly Doped Drain) structure. This LDD structure is adopted to reduce field strength in the vicinity of drain of an MOS transistor. Polycrystalline silicon film 109 containing impurities is formed to get contact with impurity-diffused region 113 of a high concentration through a contact hole 103. Electrical contact between polycrystalline silicon film 109 and impurity-diffused region 113 is made in impurity-diffused region 10 provided for contact.
In this case, since no error has occurred in the patterning by photolithography, impurity-diffused region 10 for contact lies within impurity-diffused region 113 of a high concentration. Therefore, as shown in the distribution diagram of impurity concentrations in FIG. 11, the formation of impurity-diffused region 10 for contact does not affect changes of impurity concentrations in the channel region of an MOS transistor and in its vicinity. As a result, the gradual change of impurity concentrations in the channel region of the MOS transistor and in its vicinity can be maintained. Thus, the existence of impurity-diffused region 10 does not prevent the LDD structure from reducing field strength of the MOS transistor.
However, in the case that errors have occurred in the patterning as shown in FIG. 12, impurity-diffused region 10 for contact may be formed to overlap impurity-diffused region 213 of a low concentration. In this case, impurity concentrations in the channel region of the MOS transistor and in its vicinity change sharply due to the existence of impurity-diffused region 10. As a result, the LDD structure can not exercise its effects in reducing field strength of the MOS transistor. In this manner, the lateral extension of impurity-diffused region 10 adversely affects a source/drain region of the MOS transistor, preventing the MOS transistor from maintaining its own characteristics.
While in the foregoing, description has been made on the case that the interconnection layer is formed of polycrystalline silicon film 109 containing impurities, problems as will be described below arise also in the case that the interconnection layer is formed of a high melting point metal, for example, a metal layer containing tungsten. FIG. 13 is a sectional view showing a contact structure for interconnection where errors have occurred in the patterning for forming contact holes. The interconnection layer is formed of a metal layer 191 containing a high melting point metal such as titanium and tungsten. In this case, high melting point metal layer 191 is formed to directly contact a surface 103a of impurity-diffused region 213 having a low concentration, due to the patterning errors. At this time, the high melting point metal contained in high melting point metal layer 191 is silicidized on the surface 103a of silicon substrate 1. This silicidization is more likely to occur especially when the impurity-diffused region in contact with high melting point metal layer 191 has a low impurity concentration. When the silicidization occurs, problems such as an increase in electrical resistance of the contact portion and breakdown of a junction in the impurity-diffused region arise. Thus, even when the interconnection layer is formed of a high melting point metal layer, the problems as described above occur due to errors made in the patterning.